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Transaction-level modeling (TLM) is an approach to modelling complex digital systems by using electronic design automation software.[1]:?1955? TLM is used primarily in the design and verification of complex systems-on-chip (SoCs) and other electronic systems where traditional register-transfer level (RTL) modeling would be too slow or resource-intensive for system-level analysis. TLM language (TLML) is a hardware description language, usually, written in C++ and based on SystemC library.[1] TLMLs are used for modelling where details of communication among modules are separated from the details of the implementation of functional units or of the communication architecture. It's used for modelling of systems that involve complex data communication mechanisms.[1]:?1955? The modeling approach focuses on the transactions or transfers of data between functional blocks rather than the detailed implementation of those blocks or their interconnections.[2] This abstraction enables faster simulation speeds, often orders of magnitude faster than RTL, while maintaining sufficient accuracy for system-level design decisions, software development, and architectural exploration.[3]
Components such as buses or FIFOs are modeled as channels, and are presented to modules using SystemC interface classes. Transaction requests take place by calling interface functions of these channel models, which encapsulate low-level details of the information exchange. At the transaction level, the emphasis is more on the functionality of the data transfers – what data are transferred to and from what locations – and less on their actual implementation, that is, on the actual protocol used for data transfer. This approach makes it easier for the system-level designer to experiment, for example, with different bus architectures (all supporting a common abstract interface) without having to recode models that interact with any of the buses, provided these models interact with the bus through the common interface.[4]
TLM is typically implemented using SystemC, a C++-based modeling language and library developed specifically for system-level design.[5] The Open SystemC Initiative (OSCI), now part of Accellera, has developed standardized TLM libraries that provide common interfaces and methodologies for transaction-level communication. However, the application of transaction-level modeling is not specific to the SystemC language and can be used with other languages. The concept of TLM first appears in the system-level language and modeling domain.[6]
The methodology has become essential in modern electronic design automation (EDA) flows, particularly for creating virtual platforms that enable early software development and system validation before hardware implementation is complete.[7] TLM models serve as executable specifications that bridge the gap between high-level system requirements and detailed hardware implementations. TLMs are used for high-level synthesis of register-transfer level (RTL) models for a lower-level modelling and implementation of system components. RTL is usually represented by a hardware description language source code (e.g. VHDL, SystemC, Verilog).[1]:?1955–1957?
Background and history
[edit]Early development (1990s-2000s)
[edit]Transaction-level modeling emerged in the late 1990s and early 2000s as a direct response to the increasing complexity of system-on-chip designs and the limitations of traditional register-transfer level (RTL) modeling for system-level verification and software development.[8] The semiconductor industry was experiencing a widening disparity between design complexity and designer productivity.[9]
The foundational concepts of TLM were developed simultaneously by several research groups and companies. Cadence Design Systems introduced early transaction-level concepts in their SpecC language in the mid-1990s,[10] while Synopsys developed similar concepts in their SystemC methodology starting in 1999.[11] In 2000, Thorsten Gr?tker, R&D manager at Synopsys was preparing a presentation on the communication mechanism in what was to become the SystemC 2.0 standard, and referred to it as "transaction-based modeling". Gilles Baillieu, then a corporate application engineer at Synopsys, insisted that the new term had to contain "level", as in "register-transfer level" or "behavioral level". The fact that TLM does not denote a single level of abstraction but rather a modeling technique didn't make him change his mind. It had to be "level" in order to make it stick. So it became "TLM".[citation needed]
SystemC and OSCI formation
[edit]The development of SystemC proved crucial to TLM's adoption. SystemC was initially developed by Synopsys in 1999 as a C++-based system-level modeling language.[12] In 2000, the Open SystemC Initiative (OSCI) was formed as an independent consortium to develop and promote SystemC as an open standard.[13] Founding members included Synopsys, Cadence Design Systems, CoWare, and several major semiconductor companies including ARM Holdings, Infineon Technologies, and STMicroelectronics.[14] The organization developed the OSCI simulator for open use and distribution.
Since those early days SystemC has been adopted as the language of choice for high level synthesis, connecting the design modeling and virtual prototype application domains with the functional verification and automated path gate level implementation. This offers project teams the ability to produce one model for multiple purposes. At the 2010 DVCon event, OSCI produced a specification of the first synthesizable subset of SystemC for industry standardization.
TLM 1.0 standardization (2005)
[edit]The first standardized TLM methodology, known as TLM-1.0, was released by OSCI in 2005.[15] TLM-1.0 introduced fundamental concepts including:
- Basic transaction interfaces for communication
- FIFO and signal-based communication channels
- Simple request-response transaction protocols
- Basic timing annotations
The TLM-1.0 standard was primarily focused on functional modeling and provided limited support for detailed timing analysis.[16]
TLM 2.0 evolution and IEEE standardization (2008-2011)
[edit]TLM-2.0, released in 2008, represented a major advancement in transaction-level modeling methodology.[17] The new standard introduced several key innovations:
- Generic payloads for standardized transaction representation
- Multiple timing models (untimed, loosely timed, approximately timed)
- Standardized socket interfaces for interoperability
- Enhanced debugging and analysis capabilities[18]
TLM-2.0 was subsequently incorporated into the IEEE 1666-2011 standard for SystemC, providing official recognition and broader industry acceptance.[19]
Industry adoption and commercial tools
[edit]By the mid-2000s, major EDA companies began incorporating TLM support into their commercial tools. Mentor Graphics (now Siemens EDA) introduced TLM support in their ModelSim simulator in 2004,[20] followed by Cadence Design Systems with their Incisive platform in 2005.[21] Virtual platform companies such as CoWare (acquired by Synopsys in 2010),[22] Vast Systems (acquired by Synopsys in 2007), and VaST Systems Technology contributed significantly to TLM's commercial adoption by providing high-performance virtual platforms based on TLM methodology.[23]
Modern developments (2010s-present)
[edit]The 2010s saw TLM become standard practice in the semiconductor industry, particularly for ARM-based SoC design. ARM Holdings released comprehensive TLM models of their processor architectures, including ARM Cortex-A and ARM Cortex-M series processors.[24] The rise of artificial intelligence and machine learning accelerators in the late 2010s created new demands for TLM modeling, leading to specialized libraries and methodologies for modeling neural processing units and other AI hardware.[25] In 2020, OSCI merged with Accellera, consolidating SystemC and TLM development under a single organization and ensuring continued evolution of the standards.[26]
Key Concepts
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See also
[edit]- Discrete event simulation (DES)
- Event loop
- Event-driven programming
- Message passing
- Reactor pattern vs. Proactor pattern
- Transaction processing
- Asynchronous circuit
- Assembly modelling, for CADs
References
[edit]- ^ a b c d The VLSI handbook. Wai-Kai Chen (2 ed.). Boca Raton, FL: CRC/Taylor & Francis. 2007. ISBN 978-0-8493-4199-1. OCLC 70699056.
{{cite book}}: CS1 maint: others (link) - ^ "IEEE Standard for Standard SystemC Language Reference Manual". IEEE STD 1666-2011. 2012. doi:10.1109/IEEESTD.2012.6134619. ISBN 978-0-7381-6801-2.
- ^ Ghenassia, Frank, ed. (2005). Transaction-Level Modeling with SystemC. Springer. ISBN 978-0-387-26233-4.
{{cite book}}: Check|isbn=value: checksum (help) - ^ T. Gr?tker, S. Liao, G. Martin, S. Swan, System Design with SystemC. Springer, 2002, Chapter 8., pp. 131. ISBN 1-4020-7072-1 (quoted with permission)
- ^ "SystemC Standards". Accellera Systems Initiative. Retrieved 2025-08-06.
- ^ L. Cai, D. Gajski, Transaction Level Modeling: An Overview, in proceedings of the Int. Conference on HW/SW Codesign and System Synthesis (CODES-ISSS), Oct. 2003, pp. 19–24
- ^ Schirner, Gunar (2013). Virtual Platforms in System-Level Design. Design Automation Conference. pp. 804–809. doi:10.1145/2463209.2488885 (inactive 1 July 2025).
{{cite conference}}: CS1 maint: DOI inactive as of July 2025 (link) - ^ Gajski, Daniel D. (2000). SpecC: Specification Language and Methodology. Kluwer Academic Publishers. ISBN 978-0-7923-7822-5.
{{cite book}}: Check|isbn=value: checksum (help) - ^ International Technology Roadmap for Semiconductors: Design (Report). Semiconductor Industry Association. 1999.
- ^ Gajski, Daniel D. (1997). SpecC: A Design Language for System Level Design. Design Automation Conference. pp. 464–469. doi:10.1145/266021.266138 (inactive 1 July 2025).
{{cite conference}}: CS1 maint: DOI inactive as of July 2025 (link) - ^ Gr?tker, Thorsten (2003). "SystemC: Past, Present, and Future". IEEE Design & Test. 20 (6): 72–77. doi:10.1109/MDT.2003.1246169.
- ^ "Synopsys Introduces SystemC for System-Level Design". EE Times. 2025-08-06.
- ^ "Open SystemC Initiative Formed to Advance System-Level Design" (Press release). Open SystemC Initiative. 2025-08-06.
- ^ "Accellera History". Accellera Systems Initiative. Retrieved 2025-08-06.
- ^ "OSCI Releases Transaction Level Modeling Standard" (Press release). Open SystemC Initiative. 2025-08-06.
- ^ Ghenassia, Frank, ed. (2005). "TLM-1.0 Standard". Transaction-Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems. Springer. pp. 87–124. ISBN 978-0-387-26233-4.
{{cite book}}: Check|isbn=value: checksum (help) - ^ "OSCI Releases TLM-2.0 Standard for Transaction-Level Modeling" (Press release). Open SystemC Initiative. 2025-08-06.
- ^ Aynsley, John (2009). "TLM-2.0 Reference". ASIC and FPGA Verification: A Guide to Component Modeling. Springer. pp. 145–198. ISBN 978-1-4419-0564-5.
{{cite book}}: Check|isbn=value: checksum (help) - ^ IEEE Standard for Standard SystemC Language Reference Manual (Technical report). IEEE. 2012. doi:10.1109/IEEESTD.2012.6134619.
{{cite tech report}}: Unknown parameter|standard=ignored (help) - ^ "Mentor Graphics Adds SystemC TLM to ModelSim". EE Times. 2025-08-06.
- ^ "Cadence Introduces Transaction-Level Modeling Flow" (Press release). Cadence Design Systems. 2025-08-06.
- ^ "Synopsys Acquires CoWare for Virtual Prototyping". EE Times. 2025-08-06.
- ^ Virtual Prototyping Market Analysis (Report). Gary Smith EDA. 2010.
- ^ ARM Fast Models: System-Level Modeling for Software Development, ARM Holdings, 2012
- ^ Chen, Li (2019). Transaction-Level Modeling for AI Accelerator Design. Design Automation Conference. pp. 1–6. doi:10.1145/3316781.3317788 (inactive 1 July 2025).
{{cite conference}}: CS1 maint: DOI inactive as of July 2025 (link) - ^ "Accellera and OSCI Merge to Advance System-Level Design Standards" (Press release). Accellera Systems Initiative. 2025-08-06.
External links
[edit]- SystemC.org - SystemC home page.